1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing contact holes of a semiconductor device using an etching barrier layer pattern.
2. Description of the Related Art
As the integration level of a semiconductor device becomes higher, its contact holes become smaller. Thus, high resolution photolithography is required to form the small-sized contact holes, and a misalignment margin in the photolithography is also reduced.
Particularly, a contact hole exposing a conductive region between gates of transistors, e.g., a contact hole for a bit line, or a contact hole for a storage electrode which exposes a drain and source region, must be very small to prevent an adjacent gate from being exposed. Also, the contact hole for a bit line or the contact hole for a storage electrode must be formed through one or more thick interdielectric layers. For this reason, a photoresist pattern for forming the contact hole must be also thick. However, as the photoresist pattern becomes thicker, the resolution becomes lower, making it difficult to define a desired small contact hole.
Even a slight misalignment in the photolithography process can expose the gate of the transistor adjacent to the contact hole, greatly deteriorating the performance of the semiconductor device. Thus, in forming the contact hole for a bit line or storage electrode, an etching method is widely used in which the sidewall of the contact hole has a gradient of 85-86.degree. with respect to a bottom surface of the contact hole, thereby increasing a misalignment margin.
However, in the above etching method, an etching selectivity of a silicide layer with respect to an interdielectric layer, e.g., an oxide layer, is very low. In order to reduce contact resistance and sheet resistance of a shallow junction region of the source/drain region, the silicide layer is formed on a source/drain region and a polysilicon gate using salicide (self-aligned silicide) technology. Thus, if the etching selectivity with respect to the silicide layer is low in forming the contact hole, the silicide on the source/drain region is damaged such that the sheet resistance increases.
Also, in a process of forming a semiconductor device by a 0.25 .mu.m design rule, the bit line is formed using a damascene method. By the damascene method, after forming a damascene pattern for forming a bit line, a photoresist pattern for forming the contact hole for a bit line is formed on the interdielectric layer where the damascene pattern is formed thereon. Subsequently, the photoresist pattern is flowed to reduce the size of a window defined by the original photoresist pattern, and then the interdielectric layer is etched to form a contact hole for a bit line. If misalignment in the photolithography for forming the contact hole for a bit line occurs a phenomenon in which the photoresist pattern partially hangs over the summit of sidewalls of the damascene pattern. Thus, in a process of flowing the photoresist pattern to reduce the window size, the amount of flow of the photoresist pattern covering the edge portion of the damascene pattern is different from that on a flat portion in the negative pattern, preventing the bit line contact hole from being formed or lowering the is uniformity of the bit line contact hole, and lowering the reliability of the device.